下面是关于EPM3064A 芯片特点的简要介绍：
· High–performance, low–cost CMOS EEPROM–based programmable logic devices （PLDs） built on a MAX  architecture
· 3.3-V in-system programmability（ISP）through the built–in IEEE Std. 1149.1 Joint Test Action Group （JTAG） interface with advanced pin-locking capability
– ISP circuitry compliant with IEEE Std. 1532
· Built–in boundary-scan test（BST）circuitry compliant with IEEE Std. 1149.1-1990
· Enhanced ISP features:
– Enhanced ISP algorithm for faster programming
– ISP_Done bit to ensure complete programming
– Pull-up resistor on I/O pins during in–system programming
· High–density PLDs ranging from 600 to 10,000 usable gates
· 4.5–ns pin–to–pin logic delays with counter frequencies of up to 227.3MHz
· MultiVoltTM I/O interface enabling the device core to run at 3.3 V, while I/O pins are compatible with 5.0–V, 3.3–V, and 2.5–V logic
levels
· Pin counts ranging from 44 to 256 in a variety of thin quad flat pack（TQFP），plastic quad flat pack（PQFP），plastic J–lead chip carrier
（PLCC），and FineLine BGATM packages
· Hot–socketing support
· Programmable interconnect array（PIA）continuous routing structure for fast, predictable performance
龙芯世纪专业承接IC芯片及单片机解密项目，长期以来以技术研究为主要目的，为各类电子企业及电子工程师提供解密技术支持与芯片解密研究，在国内外反向技术研究领域奠定了行业领导者的权威地位。

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